4060 is available at 74 HC4060 or 74 HCT4060 in the high-speed CMOS series. Clock frequency is 40...60 Hz (with load capacitance of 15 pF) depending on the manufacturer.

Speed and output current (fan-out)
The real advances compared with previous CMOS logic lies in the improvement of speed and fan-out which in high-speed CMOS are comparable to those in TTL. Figure 3 shows graphs of the typical gate propagation delay vs load capacitance for metal-gate CMOS, silicon-gate buffered CMOS, LSTTL and high-speed CMOS. It is clear that HCMOS is only slightly faster than LSTTL, but its smaller increase in gate-propagation delay at higher load capacitances makes for a larger increase in output current. Typical gate propagation delays in HCMOS gate are 6 ns at 10 pF, 10 ns at 50 pF, and 11.5 ns at 100 pF load capacitance.

It is also interesting to compare other logic versions of the TTL family, particularly the new 'advanced' ALS series which is two to three times faster than LSTTL. Table 1 gives a comparison of a number of typical circuits in the 74 series.

The buffered versions of the HCMOS family all have identical output stages. These are, as in CMOS, symmetrical and deliver a current of about 4 mA at both HIGH and LOW. The bus driver outputs can even supply 6 mA in both directions. Figure 4 gives a comparison between the output current levels of HCMOS and LSTTL. At LOW level output there is no difference between the output currents: both types provide 4 mA at 0.4 V. When the output is logic 1 and the supply voltage is 5 V, a HCMOS circuit delivers 4 mA at an output voltage of not less than 4.2 V while the LSTTL version provides only 0.4 mA at
not less than 2.7 V. A standard HCMOS output can, therefore, like that of 1 LSTTL, be connected to up to 10 LSTTL inputs. The fan-out with driver output is 15 LSTTL loads. In the case of HCMOS loads, the input currents (typically 1 µA) have practically no effect, so that the fan-out is limited only by the input capacitance (typically 5 pF) and not by the drive power. One output can be connected to up to 20 HCMOS inputs without any noticeable deterioration. If speed and signal-to-noise are not important, it is possible to connect up to 4000 inputs to one output. Only then, at least in theory, is an output current of 4 mA reached.

Current consumption, increase at higher switching frequencies

Lower current consumption not only reduces operating costs, but because of the reduction in heat, it also improves reliability. The quiescent current of HCMOS is, like that of CMOS, negligibly small, as, in contrast to TTL, the leakage current is of the order of only a few µA. During switching, however, internal and external capacitances have to be charged which means an increase in current. The higher the switching frequency, the higher the current consumption. In that respect, there is no difference between HCMOS and CMOS, but HCMOS circuits can switch much faster and therefore have a correspondingly higher power dissipation. The quiescent current in TTL circuits is already so high that additional current consumption becomes only noticeable at very high switching frequencies.

Figure 5 shows the basic difference between HCMOS and LSTTL. If only one circuit is considered, as in the figure, the power dissipation of HCMOS and LSTTL reaches the same value at an operating frequency of only a few MHz. A practical system, however, consists of a much greater number of ICs which in turn contain several elements such as gates, flip-flops, and the like. LSTTL circuits use the same current whatever their operation; in HCMOS only those elements which actually switch consume power. For instance, in a counter with 10 flip-flops using LSTTL circuits, all flip-flops dissipate the same power, but if HCMOS circuits were used, each flip-flop would consume only half of what the preceding one does. This fact tips the balance firmly in favour of HCMOS, as is shown in figure 6. In a standard microcomputer system with a 2 MHz or 4 MHz CPU, HCMOS circuits would use only a fraction of the power LSTTL devices do. Even in a system with a 10 MHz microprocessor, the power dissipation in HCMOS circuits would be only about one eighth of that if LSTTL devices were used.

Supply voltage, input level, and signal to-noise ratio

The supply voltage for the HC and HCU versions of the HCMOS family can vary between 2...6 V. The extension of the lower voltage limit to 2 V is particularly interesting in view of future generations of microprocessors and memories which will require a supply voltage of less than 5 V. Non-stabilized power supplies and batteries can be used without any problems, while one lithium cell or two nicad cells can serve as emergency supply.

The switching levels in HCMOS lie further apart than in LSTTL as can be seen clearly from figure 7. That means on the one hand a higher immunity to noise, but on the other that the inputs of HCMOS devices cannot be connected to the outputs of TTL circuits if the supply voltage is 5 V. ICs in the HC version can, however, be

Figure 5. HCMOS shows the same typical increase in power dissipation with switching speeds as CMOS. For a single gate the power cross-over frequency is about 5 MHz, while that for a single flip-flop lies above 10 MHz.

Figure 6. In a more complex circuit comprising a chain of 10 flip-flops, the power dissipation of HCMOS is clearly well below that of LSTTL even at the highest operating frequency.
Figure 8. The permitted supply voltage variation of ±10 per cent in the 74 HCT (TTL-compatible) series is twice that of the LSTTL. The 74 HC series can operate from supply voltages down to 2 V.

Figure 9. This shows the real improvement in input protection against electrostatic discharges in HCMOS as compared with CMOS.

Figure 7. This shows that the noise immunity of HCMOS is far superior to that of LSTTL.

combined with LSTTL types if the supply voltage is 3 V. None the less, HCT types are TTL compatible if the supply voltage is 5 V. Input levels and immunity to noise are similar to LSTTL. In contrast to the 74 LS version, the 74 HCT tolerates a supply voltage variation of ±10 per cent (see figure 8).

Compared with the already hard-wearing CMOS circuits of the 4000 family, the inputs of the HCMOS inputs are even better protected against electrostatic discharges. The input protection circuit shown in figure 9 contains a poly-silicon resistor which limits the current through the protection diode and also reduces the speed with which the current rises. The diodes themselves are also more robust than those used in CMOS ICs.

Manufacturers

HCMOS are produced by a whole series of manufacturers and, for this article, data and other information of the following were used: Philips/Valvo, RCA, National Semiconductor, Motorola, and Fairchild. The ICs produced by these manufacturers in the 74HC, 74HCT, and 74HCU series are identical in all important parameters. Agreement exists between National Semiconductor and Motorola on the one hand and Philips/Valvo and RCA on the other as to common development of HCMOS and exchange of masks. Small differences do exist in the stated values of propagation delay and maximum clock frequency. Whereas there is conformity as to gate-propagation delays with typical values of 8 to 9 ns at 15 pF loads, flip-flops and counters produced by RCA and Philips are slightly faster than those of the other manufacturers. For instance, the maximum clock frequency of the 74HC74 is typically 60 Hz (RCA) or 40 Hz (National Semiconductor) at 15 pF load. Guaranteed minimum values could not be compared owing to lack of relevant information. Table 2 shows small differences in the type coding: each manufacturer has his own prefix.

More important differences exist in the packaging: only Philips/Valvo and RCA have so far planned to manufacture their
Table 1

Gates
HCMOS
LT- TTL
ALST- TTL
S-TTL
unit

74XX00
propagation delay
8
8
5
4

74XX04
propagation delay
8
8
4
3

Multiplexer/decoder

</


13. A reference voltage is also applied to a second input of comparator 13. When the level of the output signal from peak detector 12 exceeds the reference voltage, comparator 13 will generate a signal indicating the presence of ringing, which in turn indicates that load 30 is an inductive load.

FIG. 8 shows the output waveform from filter 11 shown in FIG. 7, which is a high pass filter to reject line voltage frequency component, thus only the ringing waveform component of amplitude Vpk appears at the input to the peak detector 12.

The peak detector has an effective response time equal to several cycles of line voltage period, therefore the peak output voltage is achieved only after a corresponding number of consecutive ringing waveform events have occurred.

When the magnitude of the peak detector output exceeds the associated reference voltage, the following comparator activates a latch circuit to change the dimmer operation to leading edge mode. FIG. 8 shows the waveform of the output of the peak detector rising to a value of Vpk. FIG. 8 also shows the value of Vref in dotted lines for reference.
When the dimmer operation changes to leading edge mode the peak detector output slowly falls to zero, due to relatively slow decay time constant.

It will be understood that when this arrangement is used in a universal dimming circuit, this output may be used to trigger a known mode control circuitry to change the mode of operation of the universal dimming circuit from trailing edge to leading edge as described above.

FIG. 9 shows FIG. 4 with an additional spike detector 40. Spike detector 40 may be used in conjunction with ringing detector 10 to further enhance the performance of the arrangement of the present invention.

The circuit and the operation of the preferred embodiment of the present invention will now be described in detail with reference to FIG. 10.

The circuit of the present invention can be divided into several functional blocks as follows:

Power Transistor Drive Circuit

The load conducting elements in a typical reverse phase control dimmer comprise a pair of transistors such as MOSFET devices. Suitable gate input drive circuitry is required to provide control of switching transition time, as a means of limiting EMI (Electromagnetic Interference) emission levels (strict Standards apply in the industry to limit the level of EMI coming from devices such as dimmers).

Transistors Q9 & Q10 as seen in FIG. 5 connect in series back-to-back fashion to form an ac switch for control of the connected load. In this embodiment, transistors Q9 and Q10 are MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors), often used in power control applications. Resistors R23 & R24 assist in preventing parasitic oscillation that can occur with parallel connected MOSFETs.

Application of drive voltage to transistor R16 results in conduction of transistor Q6, which simultaneously causes transistor Q8 to be cutoff and transistor Q7 to also conduct and therefore result in activation of the load controlling ac switch.

The values of resistors R18, R19 & R20 are selected to ensure that Q7 conduction status follows that of Q6, while Q8 assumes the opposite conduction status. Q7 provides a level shifting function, while Q8 provides an inversion function.

Resistor R21 limits turn-on current via Q7 to ac switch gate input, necessary to achieve controlled leading edge switching transition times, particularly when the dimmer operation is in the forward phase or leading edge control mode.

Resistor R22 limits turn-off current via Q8 from ac switch gate input, necessary to achieve controlled trailing edge switching transition times, particularly when dimmer operation is in reverse phase control mode.

Level shifting transistor Q5, with bias resistors R13, R14 & R15 and blocking diode D6, is arranged to have conduction status opposite to that of Q6. This transistor provides an inverted pull-up drive for momentary enabling of the ringing detector circuit, which is described in more detail below.

Ringing Detector Circuit

Capacitor C1 determines, in part, the ringing signal amplitude and frequency at each mains half-cycle dimmer turn-off transition. Diodes D1 & D2, in conjunction with intrinsic inverse diodes associated with Q9 & Q10, form a diode bridge to provide full-wave rectification of dimmer voltage waveform. At each mains half-cycle turn-off transition an initially rising voltage, followed by a ringing voltage component, centered around the instantaneous mains voltage, appears at the dc side of the bridge.

At the rising dimmer voltage transition, input coupling capacitor C3 becomes charged, via series components resistor R9, diode D4 & 15V dc rail, to a level equal to the peak ringing voltage.

During the first ringing cycle, where the voltage is then falling, diode D4 becomes reverse biased while D5 is forward biased. This allows partial charge storage transfer from C3, via transistors R9, R26 & diode D5, into detector output capacitor C4—which consequently develops a negative voltage with respect to the 15V rail.

The charge delivered to detector output capacitor C4 accumulates with each mains half-cycle ringing event, with corresponding increase in capacitor voltage.

Filter input resistor R26 provides a high frequency "noise" rejection function. Resistor R27 represents loading on the dc side of the diode bridge circuit, necessary to ensure the bridge output voltage can fall at a similar rate to that of the dimmer terminal voltage. Such loading elements can be provided by current source elements for 15V rail.

Detector discharge resistor R10 has sufficient value that the rate of discharge of detector output capacitor C4 is relatively slow compared to the charging pulse repetition rate.

Diode D5 prevents discharge of detector output capacitor C4 during the rising dimmer voltage transitions. This is necessary for the "detection" function.

Resistor R25 in conjunction with input coupling capacitor C3, provides a high-pass-filter function to prevent the relatively slow falling rate of change of mains instantaneous voltage from contributing to the detector output voltage. This provides the function of block 11 in FIG. 7.

The comparator circuit 13 (see FIG. 7) comprises bias current resistor R8, reference zener diode /2 and transistor Q3. The emitter terminal of Q3 forms the comparator input, while the collector terminal forms the output.

The latch circuit 20 comprises transistors Q1 & Q2 and bias current resistors R4, R5, R6 & R7. The base terminal of Q1 forms the latch input which is driven from the comparator 13 output, while the collector terminal forms the output.

Detector disable transistor Q4, is normally biased into conduction through base current supply resistor R11. Under such conditions the charge source for detector output capacitor C4 is shunted thus disabling the ringing detector. Transistor Q5, in conjunction with capacitor C5 and resistor R11 is used to momentarily remove bias supply to Q4 at each mains half-cycle turn-off transition, thus enabling the ringing detector. This is done to minimize the susceptibility of the detector to surrounding electrical noise as previously described.

Q5 is biased by resistors R13, R14 & R15 when Q7 is not in the conducting state. In the Q7 conduction state diode D6 acts to remove base current supply for Q5.

Over-Voltage Detection Circuit

As described above, an additional function which may be implemented to enhance the function of the circuit is the use of an over-voltage, or voltage spike, detection circuit.
Dimmer operation in reverse phase control mode, when connected to highly inductive loads such as iron core transformer based neon lighting, will result in excessive voltage spiking across dimmer terminals at each mains half-cycle dimmer turn-off transition.

Turning off the switch while there is any appreciable level of current causes a sudden rise in the voltage appearing across the load. As described by the well known relationship

\[ V = L \frac{dI}{dt} \]

Where \( V \) is the voltage appearing across the inductive load;

\[ L \] is the magnitude of the inductance of the load; and

\[ \frac{dI}{dt} \] is the rate of change of the current \( I \) through the load over time \( t \)

as will be understood by the person skilled in the art.

As can be seen, the greater the rate of change in current \( I \) through the load, the greater the voltage spike occurring. It follows then that the greater current at the time of turning off the switch, which causes the current to fall to zero in a very short space of time, the greater the rate of change of current and therefore the greater the voltage spike induced.

The over-voltage detection circuit arrangement functions firstly to safely limit spiking voltage amplitude, then activate a latch circuit after spiking has been detected for a number of successive mains voltage half-cycles (for example, 3-6 half cycles).

Once triggered, the latch output status is used to signal to the dimmer control circuit mechanism that dimming operation should be changed to forward phase, or leading edge, control mode.

With reference again to FIG. 10, diodes D1 & D2, in conjunction with intrinsic inverse diodes associated with Q9 & Q10, form a diode bridge to provide full-wave rectification of dimmer voltage waveform as described above in relation to the ringing detector. The series circuit of varistor MV1 and zener diode Z1 provide the necessary dimmer terminal voltage spiking clamping function.

During clipping events, a voltage is developed across resistor R1 and detector output capacitor C2 is able to be charged via resistor R2 and diode D3. Blocking diode D3


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---

2-24 Quick Start:
Learning How to
Make Measurements
Index

A
analystor configuration, 1-8-19
analyzers with option ID5, 1-10
attaching cabinet flanges, 1-18
attaching cabinet flanges and handles, 1-19
attaching handles, 1-17
S-parameter test set, 1-9
T/R test set, 1-10
with cabinet flange kits, 1-16
with plotters, 1-11
with printers, 1-11

C
certification, iii
clock, setting, 1-15
contents of shipment, 1-2-3
accessories included, 1-2
adapters included, 1-2
cables included, 1-2
documentation included, 1-2
correction constants, 1-26

D
definitions, 2-12
return loss (dB), 2-12
return loss (T), 2-12
standing-wave-ratio (SWR), 2-12

E
EEPROM backup disk, 1-26
electrical requirements, 1-6-7
environmental requirements, 1-6-7

F
front- and rear-panel features, 1-4-5
front panel, 1-4
front-panel features, 2-2
channel keys, 2-2
display, 2-2
instrument state keys, 2-3
numeric keypad, 2-3
PRESET key, 2-3
response softkeys, 2-2
softkeys, 2-2
stimulus softkeys, 2-3

I
installation, 1-1

M
making measurements, 2-1-20
manual conventions, v
measurement procedure, 2-4
measurement sequence
choosing measurement parameters, 2-4
making a measurement calibration, 2-4
measuring a device, 2-4
outputting measurement results, 2-4

O
operation, 1-20-25
checking reflection mode, 1-25
checking transmission mode, 1-24
installed options, 1-21
operator's check, 1-23
self-test, 1-22

P
plotter configuration, 1-11-14
polar format, 2-18
printer configuration, 1-11-14
problems, data entry, 2-22
controls do not respond, 2-22
parameters not accepted, 2-22
problems, power-up, 2-21-22
display does not light, 2-21
display lights, but fan does not start, 2-21
problems, RF output, 2-22
no RF signal at either PORT 1 or PORT 2, 2-22

R
rear panel, 1-5
reflection measurements, 2-12-20
admittance, 2-20
choosing the measurement parameters, 2-13
impedance, 2-19
making a measurement calibration, 2-13
measuring a device, 2-14
measuring return loss, 2-15

Index-1
outputting measurement results, 2-15
reflection coefficient, 2-16
$S_{11}$ and $S_{22}$ in polar format, 2-18
standing wave ratio, 2-17
regulatory information, iii

S
safety considerations, general, iv
safety notes, iv
smith chart, 2-19
static-safe workstation, 1-7

T
transmission measurements, 2-5–11
3 dB bandwidth, 2-8

choosing the measurement parameters, 2-5
making a measurement calibration, 2-5
measuring insertion loss with marker functions, 2-8
measuring the device, 2-7
out-of-band rejection, 2-9
outputting the measurement results, 2-7
passband flatness, 2-10
passband ripple, 2-10
troubleshooting, 2-21–23

W
warranty, iii<|endoftext|>Contents

1 Revision History ........................................................................................................................................... 1
  1.1 Revision 1.0 ......................................................................................................................................... 1
2 Product Overview ......................................................................................................................................... 2
3 Features and Properties ............................................................................................................................ 3
4 Optical Appearance .................................................................................................................................... 4
5 Storage ..................................................................................................................................................... 5
6 Operation .................................................................................................................................................. 6
7 Power Module Replacement ..................................................................................................................... 8
8 Evaluating Thermal Properties of a Given Design .................................................................................... 9
9


 compatibility with the standard linear bipolar process. Control signals and data inputs are transistor-transistor logic (TTL) or 5-V complementary metal oxide semiconductor (CMOS) compatible, and timing is suitable for interface to most processors. The latch is level triggered; any activity on the data inputs during the enable period will cause the analog output to change. This allows the user of a single-chip microcomputer to tie the enable inputs low and sit the DAC directly on one of the latched ports already available. While several DAS, including onchip latches, are available, many of the latches are too slow to keep up with faster processors. Many also require bus data to remain stable for some time after strobing the latch, a condition which complicates the interface to 6800 type machines. The latch shown in Fig 1, however, operates in 100 ns, and has no data hold time requirement. In that it requires no negative power supply, the DACPORT is distinct from other "microprocessor compatible" DAS. It offers buffered analog output voltage ranges of 0 to 2.56 V and 0 to 10.0 V, pin selectable. The 2.56 V range is available when operating on a 4.5 V or higher power supply; the 10.0 V range can be used if the power supply is 11.4 V or higher.

The bus interface latch is straightforward; the active-low decoded address is applied to CS and the system WR connects to chip enable (CE). This connection will work in any system in which a valid address bus and a valid WR indicate valid data. When both CS and WR are low, data enter the latch; when either returns high, data are held (see Fig 2). In systems where data are valid only on clock edges, a simple one-shot will provide a usable control signal.

**ADC-Microprocessor Interface Examples**

The AD574 12-bit converter is an example of an analog to digital device. Built with standard bipolar processing, it uses IIL to implement the control and successive approximation register (SAR) functions. Microprocessor handshake capability is included in the 28-pin double-width package; an improvement over the usual 32-pin, triple-width package used for 12-bit ADCs. The device can accommodate analog
input ranges of 0 to 10 or 20 V and ±5 or ±10 V, with full-scale accuracy determined by an onboard 10 V reference.

A problem arises when 12 bits of data must be loaded into an 8-bit wide bus. Specifically, the data must be placed in two locations and accessed one piece at a time. Two possible formats can be used: left-justified, where the data indicate a fraction of the full-scale range, and right-justified, where the data represent an integral number of least significant bits (LSBs). The left-justified format also permits "coarse reads" of data in systems where an 8-bit word may momentarily provide sufficient resolution. Arithmetic is not hindered by left-justified data as long as the programmer recognizes that the data represent a binary fraction.

Interfacing an ADC to a microprocessor requires a slightly different control sequence than interfacing a DAC to a microprocessor. First, the processor must tell the converter when to begin converting. Usually a WRITE address is decoded to provide the START pulse and one or more READ operations are needed to place the converted data on the bus. Also, since few integrated circuit ADGs (certainly none over eight bits) can convert during a single instruction, a STATUS output is required to indicate whether the converter has completed its cycle. This signal can be read and tested by the microprocessor or used as an interrupt in the case of a very slow converter (millisecond or longer conversion times). Alternately, the program can execute sufficient dummy instructions to timeout the converter's maximum conversion time. Fig 3 shows such a handshaking arrangement.

The AD7581 is a CMOS device which includes an 8-channel, 8-bit continuous-cycling ADC and 8 bytes of random access memory (RAM), both controlled by a built-in direct memory access controller. The processor thus sees only eight...
memory locations with up-to-date results from each of the eight internal ADC channels. The block diagram of the device (Fig 5) shows the high level of digital and analog integration on the chip.

Of the successive approximation type, the ADC completes a scan of all eight channels in 500 $\mu$s. As a channel is converted, the 8-bit result is deposited in the onchip RAM. Internal logic prevents the update from occurring during memory READ cycles. A single clock signal, which can be the system clock in 6800 or 6502 type processors, is required; address latch enable (ALE), while not necessarily symmetrical, can be used in 8085 type systems. In systems such as the 8085, which use a single bus to carry data and the least significant address bits, the onboard address latch can be used and is driven by ALE. If the address latch is not needed, ALE can be tied high, thus rendered transparent. Access time of the CMOS RAM is 250 ns. Total device power requirement is 40 mW for a 5-V supply.

Conversion is totally independent of central processing unit operations. It is continuous, with a status line providing a short negative-going pulse to signify a channel update. This pulse is extended when the last channel is converted, so that systems can detect when an 8-channel scan is completed.

Summary

Microprocessor compatibility with conversion devices is presently obtained by three methods. In the first, no interface is added, and the user is required to custom-build his own. The compromise method allows some user flexibility, but vital functions are onchip. With the processor transparent method, conversion, handshaking, and storage are all integrated on a single chip.
Single-Chip Digital Correlator
Compares Stored 64-Bit Reference Word

A single-chip correlator that replaces 40 to 50 SS/MSI devices compares a stored 64-bit reference word with an incoming 64-bit serial word at a rate of 20 MHz. The total number of bit for bit agreements between the reference and incoming data are indicated by a 7-bit, binary weighted output. TDC1023, introduced by TRW LSI Products, 2525 E El Segundo Blvd, El Segundo, CA 90245, meets requirements of digital signal processing systems where signal patterns are compared. Correlation is widely used to detect a desired signal in the presence of other signals or noise, to identify specific signal patterns, and to measure time delays through various mediums.

Operation of the device is centered around four 64-bit, independently clocked 40-MHz shift registers. Incoming data are clocked into the A register. The reference word is entered into the B register and then parallel dumped in the R register, allowing the user to serially load a new reference word into the B register while correlation takes place between the A and R registers. An M, or mask register, permits the user to select bit positions where no comparison is desired.

Data in the A and R registers are continually compared bit for bit by exclusive OR gates, whose outputs are applied to a digital summer via AND gates. The output of the digital summer is a 7-bit word that represents the binary weighted sum of the bit positions in the A and R registers that are in agreement. The mask register allows the user to work words of less than 64-bits and to eliminate bit positions of no interest. This register is employed by inserting logical 0s in the no comparison bit positions. Masked bits are prevented from reaching the digital summer because the outputs of the M register are applied to AND gates that also contain outputs from the exclusive-OR gates.

Either true or inverted binary outputs can be obtained from the correlator through use of the INV control line, which is applied to seven exclusive-OR gates that accept outputs from the digital summer. Outputs from gates are applied to 3-state output buffers controlled by a signal TRI. Logical 1 applied to TRI disables the buffered outputs by placing them in their high impedance state. When INV is a logical 1, the output lines are inverted and when INV is logical 0, they are true.

A correlation threshold, indicated by flag T, can be established with the independently clocked, 7-bit T register. This is accomplished by first placing the output lines (D₀ to D₆) in their high impedance state through the use of TRI. Then these output lines can be used to insert the binary weighted threshold number into the T register.

When the binary weighted number from the digital summer is equal to or greater than the threshold number stored in the T register, flag T becomes a logical 1, showing that the threshold conditions have been met.

Expansion of correlation codes in multiples of 64 bits can be accommodated using the Aₒᵤₜ, Bₒᵤₜ, and Mₒᵤₜ lines available on each chip. These outputs are applied to the corresponding Aₒᵳ, Bₒᵳ, and Mₒᵳ lines of the succeeding chip. With this arrangement an external digital summer must be used to obtain the final sum, a function obtained by a binary adder. Also, an external IC equivalent of the threshold register must be used if that function is desired. The maximum number of correlators that can be used in cascade is limited by the loading and speed of the external circuits. The device is housed in a 24-pin DIP and operates from a single 5-V supply. Inputs and outputs are TTL compatible.

Circle 441 on Inquiry Card


motors are unique in that they will still work when the two connections are reversed. They will just spin in the opposite direction when hooked up backward. To keep things simple, always think of the red wire as positive (+) and the black wire as negative (-).

**MEET YOUR MOTOR CONTROLLER.**

The TB6612FNG Motor Driver may look complicated, but it’s easy to use. Three pins on the right (PWMA, A12 and A11) control the two pins on the left (A01 and A02). The same is true for channel B. Motors require more current, which is why the VIN voltage is needed.

Most ICs have polarity and usually have a polarity marking in one of the corners. The motor driver is no exception. Be sure to insert the motor driver as indicated in the circuit diagrams. The motor driver pins are explained in the table on the next page.

PIN LABEL
FUNCTION
POWER/INPUT/OUTPUT
NOTES

VM
Motor Voltage
Power
This is where you provide power for the motors (2.2V to 13.5V)

VCC
Logic Voltage
Power
This is the voltage to power the chip and talk to the microcontroller (2.7V to 5.5V)

GND
Ground
Power
Common Ground for both motor voltage and logic voltage (all GND pins are connected)

STBY
Standby
Input
Allows the H-bridges to work when high (has a pull-down resistor, so it must actively be pulled high)

AIN1/BIN1
Input 1 for channels A/B
Input
One of the two inputs that determine the direction

AIN2/BIN2
Input 2 for channels A/B
Input
One of the two inputs that determine the direction

PWMA/PWMB
PWM input for channels A/B
Input
PWM input that controls the speed

A01/B01
Output 1 for channels A/B
Output
One of the two outputs to connect the motor

A02/B02
Output 2 for channels A/B
Output
One of the two outputs to connect the motor

HOOKUP GUIDE

READY TO START HOOKING EVERYTHING UP? Check out the circuit diagram and hookup table below to see how everything is connected.

**CONNECTION TYPES**

- **REDBOARD CONNECTION**
- **BREADBOARD CONNECTION**

**JUMPER WIRES**

- 5V to 5V
- GND to GND (-)
- VIN to A1
- D8 to J7
- D9 to J6
- D10 to J5
- D11 to J3
- D12 to J2
- D13 to J1
- D7 to I27
- 5V (+) to 5V (+)
- GND (-) to GND (-)
- A2 to 5V (+)
- A3 to GND (-)
- J4 to 5V (+)
- I26 to GND (-)

**MOTOR**

- A4 (RED +)
- A5 (BLACK -)

**MOTOR DRIVER**

- C1-C8 to G1-G8 (VM on C1, PWMA on G1)

**SWITCH**

- F25
- F26
- F27
Open the Arduino IDE

Connect the RedBoard to a USB port on your computer.

Open the Sketch:
File > Examples > SIK_Guide_Code_V_4 > CIRCUIT_5A-MOTOR BASICS

Select UPLOAD to program the sketch on the RedBoard.

WHAT YOU SHOULD SEE
Flip the switch. The motor will spin at the speed set by the motor speed variable (default is 0). Open the Serial Monitor, type any number from 130 to 255 or -130 to -255, and then press Enter. Changes in speed will be hard to notice. Send 0 to stop the motor.

PROGRAM OVERVIEW

1. Check to see if a command has been sent through the Serial Monitor. If a command has been sent, then set the motor speed to the number that was sent over the Serial Monitor.

2. Check to see if the switch is ON or OFF.
   A: If the switch is ON, drive the motor at the motor speed.
   B: If the switch is OFF, stop the motor.

CODE TO NOTE

PARSING INTEGERS:
Serial.parseInt();

.parseInt() receives integer numbers from the Serial Monitor. It returns the value of the number that it receives, so you can use it like a variable.

SERIAL AVAILABLE:
Serial.available();

This command checks how many bytes of data are being sent to the RedBoard. If it is greater than 0, then a message has been sent. It can be used in an if statement to run code only when a command has been received.
**CODING CHALLENGES**

**MAKE THE SWITCH CHANGE DIRECTIONS:** Change the code so that the position of the switch changes the direction of the motor instead of turning it on and off.

**REPLACE THE SWITCH WITH A BUTTON:** Try wiring a button into the circuit instead of the sliding switch. Now the motor only turns on when you push the button.

**REPLACE THE SWITCH WITH A SENSOR:** Try changing the code so that the motor is activated by another sensor, like the photoresistor.

---

**TROUBLESHOOTING**

**Motor not spinning**
Check the wiring to the motor driver. There are a lot of connections, and it’s easy to mix one of them up with another. Double check the polarity of the motor driver. All the text should face the same direction as everything else.

**Switch not working**
Make sure that you are hooked up to the middle pin and one side pin on the switch, and not both side pins.

**Still not working?**
Jumper wires unfortunately can go “bad” from getting bent too much. The copper wire inside can break, leaving an open connection in your circuit. If you are certain that your circuit is wired correctly and that your code is error-free and uploaded but you are still encountering issues, try replacing one or more of the jumper wires for the component that is not working.

---

You’ve completed **Circuit 5A**!
Continue to **Circuit 5B** to construct a remote-controlled robot.
In this circuit, you’ll control two motors and build your own remote-controlled roving robot! You will also learn how to read information from a serial command so that you can use the Serial Monitor to tell the robot in what direction to move and how far to move.

NEW CONCEPTS

**ASCII CHARACTERS:** ASCII is a standard for character encoding, formalized in the 1960s, that assigns numbers to characters. When typing on a computer keyboard, each character you type has a number associated with it. This is what allows computers to know whether you are typing a lowercase “a,” an uppercase “A” or a random character such as ampersand (&). In this experiment, you will be sending characters to the Serial Monitor to move your remote-controlled robot. When you send a character, the microcontroller is interpreting that as a specific number. ASCII tables available online ([http://sfe.io/ASCII](http://sfe.io/ASCII)) make it easier to know which character is represented by which number.

**CONVERTING STRINGS TO INTEGERS:** String variables hold words like “dog” or “Robert Smith” that are made up of multiple characters. Arduino has a set of special built-in methods for string variables that you can call by putting a period after the variable name, as follows:

```java
string_variable_name.toInt();
```

The `.toInt()` method converts the string to a number, and there are a dozen other methods that can do things like tell you the length of a word or change all of the characters in a string to uppercase or lowercase.

**ASSEMBLY**

Before you build this circuit, you’ll need to make a few modifications to the breadboard baseplate to make it more robot-like!

1. Cut and attach two short pieces of Dual Lock tape to the very corners of the baseplate on the side located under the breadboard.
2. **CUT TWO MORE STRIPS** that are 1.25 inches (3.175cm) long and ¾ inch (1.9cm) wide. Remove the adhesive backing, and attach the strips to the two motors. Be sure that your motors are mirror images of each other when you attach the Dual Lock.

3. **PRESS THE MOTORS TO THE BASEPLATE**, connecting the two Dual Lock surfaces. Try to get the motors as straight as possible so your robot will drive straight.

4


all connections to the Control and Drive boards at this time. Proceed to section 7 Initial Power Up and Test.
6.2 Replacing MOVFR-0069N

• Remove the Control Board and Drive shown in Figure 17 - MOVFR-0069N
• Mount and secure the ECI MOVFR-LCD Control board and Drive board as shown in Figure 18 - ECI MOVFR-LCD Installed.
• Connect communication cable (CAT5) between Control and Drive Boards.
• Make all connections to the Drive and Control boards at this time and proceed to Section 7 Initial Power Up and Test.

Figure 16- MOVFR-00069N Installation Kit

Figure 17 - MOVFR-0069N

Figure 18 - ECI MOVFR-LCD Installed
7 Initial Power Up and Test

7.1 Manual Operation

- With the doors in the fully closed position and the AUTO/MAN switch in the MAN position, apply power to door operator
  - LCD Display should show

    | Edit parameters |
    |-----------------|
    | Load defaults   |
    | Diagnostics 1   |
    | Diagnostics 2   |

  - Check that the POWER on the display board and PWR LED on the drive board are lit.
  - Check that the COM, and BRAKE LEDs on the drive board are lit.
- Press Enter Button to select EDIT PARAMETERS
- Press – button until INPUT VOLTAGE is highlighted.
- Press ENTER button and set to proper input voltage using + button. Press ENTER then ESC buttons when complete.
- Move cursor down to DIAGNOSTICS 1 and press ENTER
  - LCD should show

    | VBUS : 317V 0s |
    | SPEED : 0      |
    | TEMP : 29C/ 84F|
    | MOTOR : .0A    |
    | CYCLE : xxxx   |

  - NOTE that the VBUS and TEMPs are estimates
- With the AUTO/MAN switch in MAN position set the CLOSE/OPEN switch to the OPEN position. (If motor moves in wrong direction, remove power from unit and swap 2 or the 3 motor leads.)
  - The SPEED and MOTOR readings should increase as the door moves.
  - Hold switch until door is fully open and the DOL LED lights.
    - When fully OPEN the SPEED and MOTOR reading should go to 0 even with the switch in OPEN position.
8 Adjustments

At this time adjustments can be made through the parameter settings to produce smooth door operation and adjust OPEN and CLOSE torque settings. Refer to section 8.1 for speed profiles and CAM settings.

NOTE - For HEAVY DOOR adjustments the elevator car must be at a “heavy door” floor. When moving a heavy door in MAN operation the HEAVY switch must be used with the CLOSE and OPEN switches.

**NOTE:** IT IS IMPORTANT TO RETURN THE DISPLAY TO THE MAIN MENU WHEN ADJUSTMENTS ARE COMPLETE. FAILING TO DO SO WILL RESULT IN PARAMETERS REVERTING TO DEFAULT SETTINGS SHOULD POWER BE LOST.

8.1 Speed Profiles

8.1.1 Closing Speed Profile
8.1.2 Closing CAM/Sensor Sequence

Figure 20 - Close CAM/Sensor Sequence

8.1.3 Open Speed Profile

Figure 21 - Open Speed Profile

8.1.4 Open CAM/Sensor Sequence

Figure 22 - OPEN CAM/SENSOR Sequence
8.2 CAM Settings

8.2.1 Right Hand CAMs

8.2.2 Left Hand CAMs

9 AUTO Operation

- Go to EDIT PARAMETERS and change the INPUT VOLTAGE parameter to the proper voltage for your system.
- Switch the AUTO/MAN switch to AUTO position.
- Door operator is now ready for normal operation.<|endoftext|>Note

The LED & button mentioned through this document is at the back of the accessory, above the power jack/cable
Full Instructions

Requirements

- HK Garage App Link Play Store App Store
- Garage Door Accessory, power cable, and adapter
- Tilt sensor and battery

Hardware button input and LED indicators:

The LED & button mentioned throughout this document is at the back of the device, near the power jack/cable

1. **Button:**
   a. To reset the device to factory settings: Press and hold the button for 10 seconds
   b. To remove current wifi information stored on the device: Press and hold the button for 3 seconds.

2. **LED states meaning table:**

Color
State
Meaning

Orange(Red)
Blink rapidly every 200ms
Ready to Add to an account if device is brand new or after board is factory reset

Wifi configuration has changed on Home App (If device is already added to an account)

Solid
Blink slowly each 3 seconds
Working normally

Red
Blink on/off each 500 ms
Device can connect to the wireless network, but has not been added to an account.

Red
Blink on/off each 1 second
Connecting to available network.

Firmware update is in progress.

Instruction steps

1. Hardware setup
   a. Plug garage accessory into an AC outlet
   b. If the LED blinks orange (red) rapidly, the accessory is ready to accept new wifi configuration. Please proceed to the next step.

2. Account registration and setup
   a. Install & open HK Watchman Garage Door app from the App Store (iOS)
   b. On the login screen, choose Sign up to create a new account
   c. Choose your username, email, and password. Then press Sign up to complete.
   d. Activate the registration email in your Inbox, please also check Spam or Junk if there is no registration email
   e. Login with the registered email and password
   f. When logged in successfully, you will be redirected to the Home screen.
   g. Click on the menu icon on the top left of the Home Screen to open a side menu.
   h. Click on the Add Home button on this menu to add a new home. Name the home. Verify that the home appears under My Homes on the side menu
   i. You have completed the account setup. Please proceed to the next step

3. Gateway accessory & app configuration
   a. In the Home screen above, after a home is created, tap on the “+” button on the toolbar or the Add Product button to go to the Add Product screen
   b. Select your device which will show up as “Watchman xxxx”
c. You’ll have the option to add the garage device either by using the camera to capture the QR code sticker on the side of the device or enter the code below the QR code on the sticker.
d. When the accessory is successfully added, there will be a dialog to notify you of the event and the app will bring you back to the Home Screen. The accessory will now be solid orange (red).
e. The accessory now displays on the home screen but is not yet functional since we haven't paired a tilt sensor with it. To assign a remote to an accessory, select on the top right corner of the accessory.
f. Scroll down and click on Pair sensor. A dialog will pop up.
g. On the tilt sensor, press and hold the button (circled in red below) until the LED (circled in blue) blinks red. Then, press Done on the dialog.

(figure 1)
h. The app will notify you of the outcome of the pairing process.
i. You can now go back and control the garage. To open, swipe up, to close, swipe down. Refer to the section below on the orientation of the tilt sensor and how to attach it to your garage door.

**Instructions on Orientation of the tilt sensor**

To simulate the open/close state of the garage door without having one, turn the tilt sensor to the corresponding open/close position of your desire.

**Close state:**

The arrow points up like in this image (figure 2)
Open state:

The arrow points in (to the house) horizontally
The side shows in figure 1 will face downwards (the ground)
Instructions on attaching the Tilt Sensor to the garage door

Attach the side without the buttons to the top panel of the garage door, with the arrow pointing up, such that when the garage door is fully open, the arrow will point into the house and the side with the buttons will face the ground.

Optional: Virtual Keypad

Virtual keypad is a web application which appears on the phone's browser when a user uses its camera to scan the Doorbell QR Code/NFC tag. The virtual keypad allows the scanner to control the garage door with an access-code shared by the owner of the garage door, meant for guests which don't have our app available. The access code can be configured to be used only 1-time, within a limited time period, etc. and can be revoked anytime by the owner. In addition, the virtual keypad can acts as a virtual doorbell to anonymously contact the homeowner via phone notification, message chat, or video call.

A. How to setup Virtual Keypad Via Doorbell QR Code/NFC tag

1. Install ReachMe app: [Apple


$n$ & **maximize** BW

$$A_0 = A_{\text{tot}} \Rightarrow A_0 = A_{\text{tot}}^{\frac{1}{\nu n}}$$

$$W_{\text{on}} = \frac{W_n}{A_{\text{tot}}} \cdot \sqrt{\frac{1}{2^{\nu n} - 1}}$$

apply $\frac{dW_{\text{on}}}{dn} = 0$

After some algebra:

$$n_{\text{opt.}} = \frac{\ln 2}{\ln \left\{1 + \frac{\ln 2}{2 \ln A_{\text{tot}}}\right\}}$$

For large $A_{\text{tot}}$,

$$\ln \left\{1 + \frac{\ln 2}{2 \ln A_{\text{tot}}}\right\} \approx \frac{\ln 2}{2 \ln A_{\text{tot}}}$$

$$\ln(1 + x) \approx x \text{ for } x \ll 1$$

$$\Rightarrow n_{\text{opt.}} \approx 2 \frac{\ln A_{\text{tot}}}{\ln 2}$$
optimum gain/Stage:

\[ A_{0,\text{opt}} = (A_{\text{tot}})^{\frac{1}{\gamma_{\text{opt}}}} = \exp \left\{ \frac{1}{\gamma_{\text{opt}}} \ln A_{\text{tot}} \right\} \]

\[ \approx e^{\frac{1}{2}} \]

\[ A_{0,\text{opt}} = \sqrt{e} \]

optimum BW:

\[ \omega_{n,\text{opt}} = \frac{W_n}{A_{\text{tot}}^{\frac{1}{\gamma_{\text{opt}}}}} \sqrt{\frac{1}{2} \gamma_{\text{opt}} - 1} \]

\[ \approx \frac{W_n}{\sqrt{e}} \left[ \exp \left\{ \frac{1}{\gamma_{\text{opt}}} \ln 2 \right\} - 1 \right]^{\frac{1}{2}} \]

\[ \omega_{n,\text{opt}} \approx W_n \sqrt{\frac{\ln 2}{2e \ln A_{\text{tot}}}} \]

\[ \omega_{n,\text{opt}} \approx \frac{0.357 W_n}{\sqrt{\ln A_{\text{tot}}}} \]

In other words,

* \( BW \times \sqrt{\ln a} = \text{constant} \)

* If \( A_{\text{tot}} \to A_{\text{tot}} \times 100 \), \( BW \to < BW \times 2 \)

* Overall amp does not have constant \( G \times BW \) product (obviously, be cause \( G \times BW \) is constant only for single-pole systems)
* Gain product for this cascaded amp

\[ G = A_{\text{tot}} \cdot W_0 \]

\[ = A_{\text{tot}} \cdot \frac{0.357W_0}{\sqrt{\ln(A_{\text{tot}})}} \Rightarrow \text{increases without bound} \]

---

**Gain-bandwidth-delay Tradeoff**

* Delay is less important in systems with 1-way comm. (e.g. TV, optical fibre comm.)
* Coupling between A & BW is weak for higher order cascaded systems
* If delay can be arbitrary, what A or B can be achieved?

---

* Recall: \( BW \propto \frac{1}{\text{rise time}} \)

* Imagine an amp that stores energy in input step for a long time, then dumps it suddenly into an output \( \Rightarrow \) very fast rise time \( \Rightarrow \) high BW

**Distributed Amplifier** (Travelling Wave Amp.)

![Distributed Amplifier Diagram](image-url)
* inputs to transistors supplied by tapped delay line
* output fed into another tapped delay line
* assume input has a voltage step.
  → after a delay through each line, it appears at transistor inputs
  → each transistor generates current equal to \( g_m \times \text{input step} \)
  → currents of all transistors sum coherently in time, if delays of input & output line are matched

* at each point of the tapped delay line,
  \[ \text{Zin} = \frac{Z_0}{2} \]

* overall gain \( Av = \frac{n \cdot g_m \cdot Z_0}{2} \) for \( n \) stages

→ \( Av \propto n \)
→ \( Av > 0 \) if \( g_m > 0 \)
→ BW does not factor directly into tradeoff
→ assume that \( C_{in} \&\ C_{out} \) of transistors are absorbed into \( RLCG \) of TDL
→ \( C_{in} > C_{out} \) ⇒ matching between TDLs is difficult \( \{ C_{gs} > C_{db} \} \)
* Can be power-hungry
* TDLs can be replaced by lumped LC equivalents (artificial T-lines)
* Main advantage: You can achieve significant gain @ freq. close to \( f_r \)
* High gain & low NF not possible
* Area is large
* \( Z_0 \)'s for G & D T-lines need not be the same
* If T-lines are lossy, \( A_v \to 0 \) as \( N \to \infty \)

\[ \text{Vin in gate line decays exponentially} \]
\[ \Rightarrow A_v \text{ increases linearly with } n \]
\[ \Rightarrow n_{opt.} \text{ exists for a given set of TDL's and MOSFETS.} \]

**Artificial T-lines**
* Has BW limitation because of lumped LC (ideal lossless TDL has no BW limitation)
* \( T_{delay} = \sqrt{LC} \text{ per LC-section} \)
* (Ideal TDL \( T_{del.} = \sqrt{LC} \cdot z \), \( z=\text{length} \))
\[ Z_{in} = j \omega L \frac{1}{2} \left[ 1 \pm \sqrt{1 - \frac{4}{\omega^2 LC}} \right] \]

\[ \Rightarrow \text{cutoff} = \frac{2}{\sqrt{LC}} \quad \text{cutoff frequency} \]

* Choose \( LC \) for

  \[ \Rightarrow \text{min. loss & attenuation} \]

  \[ \Rightarrow \text{cutoff } > \text{required BW} \]

  \[ \Rightarrow \text{desired } T_{\text{delay}} \]

  \[ \Rightarrow \text{constant group delay (min. dispersion)} \]

* for a lossy line, constant G.D. \( \Rightarrow RC = CL \)

\[ \Rightarrow \frac{1}{\tau} = \frac{C}{L} \quad \text{equal time constants} \]<|endoftext|>Identifying ValueRAM Memory Modules

This reference guide is designed to help you identify our ValueRAM® memory modules by specification. While this is a representation of a majority of our generic modules, naming conventions may vary as necessary. The back page is a summary of the terms used to describe these industry-standard modules.

### DDR3 for Desktops and Servers (PC3-8500, PC3-10666)

ValueRAM
Module Code
Type
Chip Type
Speed
Capacity
Special Designators

KVR 1066
D3 D 4 R 7 S K2/4G
Registered
Registered
1333
4GB
Intel Validated

### DDR2 for Notebooks, Desktops, and Servers (PC2-3200, PC2-4200, PC2-5300, PC2-6400)

ValueRAM
Module Code
Type
Chip Type
Speed
Capacity
Special Designators

KVR 400
D2 D 8 N 3 H K2/512
Registered
Registered
667
4GB
Intel Validated

### DDR for Servers (PC2700, PC3200)

ValueRAM</th


erclockwise. This will prevent audio from being transmitted but will not affect VX-1 during initial adjustments.

4. Place the VOX PTT switch in the VOX position.

5. While speaking into the microphone in a normal manner, slowly rotate the VOX GAIN control clockwise until the VX-1 keys the transmitter. Do not use more VFO GAIN than necessary to assure positive operation of normal voice levels.

6. Increase the receiver gain until received signals are at a normal volume level. These signals will trip the Vox when picked up by the microphone.

7. With the microphone held in the normal operating position, very slowly increase the ANTI-VOX until received signals do not trip the Vox.

NOTE: Excessive ANTI-VOX gain will cause received signals to gole the VX-1 off so that no amount of sound at the microphone will key the transmitter. Satisfactory balance between the VOX GAIN and ANTI-VOX is easily obtained when the microphone is at least a foot from the speaker.

8. Adjust the DELAY control to hold the transmitter keyed for the desired interval after you stop talking.

NOTE: A little experimenting on the air will reveal that only a small portion of the first spoken syllable is left when the VX-1 is actuated. Short DELAY settings will result in most efficient operation.<|endoftext|>Description

The KP25x integrated pressure sensor family is a miniaturized Digital Barometric Air Pressure Sensor IC based on the capacitive principle. It is surface micro-machined with a monolithic integrated fully digital signal conditioning circuit, implemented in state-of-the-art 0.5 micron BiCMOS technology. The KP25x provides an SPI interface to enable direct microcontroller connections with a minimum bill of materials.

The KP25x is individually calibrated and temperature compensated, reducing software complexity by providing a direct readout of pressure and temperature. KP25x provides a fast startup time of less than 10 ms, high accuracy of up to 1 kPa and different sensitivities. Combined with the wide operating temperature range of -40 to 125 °C, high ESD robustness, and excellent EMC performance, the KP25x is perfectly suited to the harsh environmental conditions prevalent in automotive and industrial applications.

Features

- High accuracy pressure sensing up to +/- 1.0 kPa
- Integrated temperature sensor
- Pressure ranges 40-115 kPa and 60-165 kPa
- Wide operating temperature range -40 to 125 °C
- Digital SPI interface
- Up to 12 bit pressure and temperature resolution
- Calibrated and compensated
- Self-diagnosis features
- Fast startup time of less than 10 ms
- „Green“ 8 pin SMD housing

Typical Applications

- Automotive Engine Management
- Small Engine Management
- Industrial Control
- Altimeter
- Weather Station
- Medical

KP25x Application Circuit

www.infineon.com/pressure
KP25x Integrated Pressure Sensor
Digital Barometric Air Pressure Sensor IC

INFINEON TECHNOLOGIES offers an extensive product portfolio for gasoline and diesel engine management systems and industrial control applications. Our products range from micromachined sensors, microcontrollers, and smart power ICs to voltage regulators and other standard components. The KP25x is a digital integrated pressure sensor for barometric pressure management, and provides benchmark performance in terms of reliability, accuracy, and ease-of-use.

Parameter
KP253
KP254
KP256
Unit

Pressure range
60.0 - 165.0 kPa
40.0 - 115.0 kPa
60.0 - 165.0 kPa
kPa

Accuracy
+/- 1.0 kPa
+/- 1.5 kPa
+/- 1.0 kPa
kPa

Output Format
Digital SPI
Digital SPI
Digital SPI

Resolution
12 bits
10 bits
10 bits
bits

Sensitivity
39 LSB/kPa
13.6 LSB/kPa
9.8 LSB/kPa
LSB/kPa

Supply Voltage
3.3 - 5.0 V
3.3 - 5.0 V
3.3 - 5.0 V
V

Order Code
SP000843708
SP000773948
SP000773952

ATTENTION PLEASE!
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.

INFORMATION
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).

WARNINGS
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.<|endoftext|>Summary

The Intel® Multi-Channel Streaming DMA Controller IP provides a small footprint, highly efficient solution for FPGA designs.

This IP Core offers both memory-based DMA for handling transfers to and from addressed memory such as on-board SRAM and SDRAM, and FIFO-based DMA for streaming applications.

Intel's DMA Controller and reference design applications provide the complete solution for rapid inclusion of fast PCI Express data transfers and streaming into FPGA environments. Additionally, Intel's generic software API is platform-independent thus enabling auto-discovery of applications and helping provide a route to the unique PCI identification of the final product.

Key Features

- PCIe-based DMA Controller firmware
- 64, 128 and 256-bit PCIe interface support:
  - PCIe Gen1, Gen2, Gen3 support (dependent on FPGA family)
  - 1 & 2, 4 or 8 PCIe lane support options
- PCIe 8-lane Gen3 supports up to four UHDTV1 (3840 x 2160 p60 video streams.
- Offers both streaming FIFO-based DMA and memory-based DMA channels
- Highly efficient use of PCIe bandwidth, making it particularly suited to data streaming applications
- Support for multiple outstanding read requests
- Pre-fetching of Scatter-Gather descriptors for continuous streaming
- Optimised arbiter for back-to-back packing of Transition Layer Packets (TLP)
- Configurable number of 32, 64 or 128bit FIFO-based DMA streaming channels
- Supports 32-bit or 64-bit addressing
- Free 30-day evaluation
Applications

The Intel Multi-Channel Streaming DMA Controller IP can be used in a range of applications including:

- Video to PCI conversion
- Video capture and storage
- Video analysis

The associated application demonstrates the ability of the DMA controller to simultaneously read and write multiple input video streams. It can work with SD, HD or 3G video. The application also demonstrates the use of the Windows driver and API supplied with the DMA Controller.

Product Options

- 1 & 2, 4 or 8 PCI Express Lane support
- Streaming FIFO-based DMA support
- Number of DMA channels (up to 16)
- FPGA family
- QT application providing register/write DMA functions, source code
- Intel Generic API and Driver source code
- Extended evaluation period (over 30 days)
- Extended support period (over 1 year)

Design Your Product Today with Intel FPGAs

Intel provides a large range of complementary and modular in-house IP cores for video processing and connectivity. These IP cores can be used to create complete solutions for applications in Broadcast, ProAV, Aerospace/Defense, Medical, Automotive and more.

You can get more information on available video IP at www.intel.com/fpga-broadcast or contact an Intel sales representative for further inquiries.<|endoftext|>KEYSTROKE TACTILITY ARRANGEMENT ON A SMOOTH TOUCH SURFACE

Inventor: Wayne Carl Westerman, San Francisco, CA


46
146
646
146

523.xalancbmk_r
72
314
242
314
242
315
241

525.x264_r
72
276
456
276
457
278
453

531.deepsjeng_r
72
435
190
433
191
433
191

541.leela_r
72
646
184
655
182
647
184

548.exchange2_r
72
402
470
400
471
401
470

557.xz_r
72
518
150
518
150
517
151

*Results appear in the order in which they were run. Bold underlined text indicates a median measurement.*

Submit Notes

The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file.

Operating System Notes

Stack size set to unlimited using "ulimit -s unlimited"

General Notes

Environment variables set by runcpu before the start of the run:
LD_LIBRARY_PATH = "/home/cpu2017/lib/intel64:/home/cpu2017/lib/ia32:/home/cpu2017/je5.0.1-32"

Binaries compiled on a system with 1x Intel Core i9-7900X CPU + 32GB RAM memory using Redhat Enterprise Linux 7.5
Transparent Huge Pages enabled by default
Prior to runcpu invocation
Filesystem page cache synced and cleared with:
sync; echo 3>/proc/sys/vm/drop_caches
runcpu command invoked through numactl i.e.:
numactl --interleave=all runcpu <etc>
NA: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented.
Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented.
Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2)
Cisco Systems
Cisco UCS B200 M5 (Intel Xeon Gold 6240M, 2.60GHz)

SPECrater®2017_int_base = 227
SPECrater®2017_int_peak = Not Run

CPU2017 License: 9019
Test Date: Aug-2019
Test Sponsor: Cisco Systems
Hardware Availability: Apr-2019
Tested by: Cisco Systems
Software Availability: May-2019

General Notes (Continued)

is mitigated in the system as tested and documented.

Platform Notes

BIOS Settings:
Intel HyperThreading Technology set to Enabled
SNC set to Enabled
Power Performance Tuning set to OS Controls
Patrol Scrub set to Disabled
Sysinfo program /home/cpu2017/bin/sysinfo
Rev: r5974 of 2018-05-19 9bcede8f2999c33d61f64985e45859ea9
running on linux-db10 Wed Sep 4 15:10:41 2019

SUT (System Under Test) info as seen by some common utilities.
For more information on this section, see
https://www.spec.org/cpu2017/Docs/config.html#sysinfo

From /proc/cpuinfo
 model name : Intel(R) Xeon(R) Gold 6240M CPU @ 2.60GHz
  2 "physical id"s (chips)
  72 "processors"
 cores, siblings (Caution: counting these is hw and system dependent. The following
 excerpts from /proc/cpuinfo might not be reliable. Use with caution.)
 cpu cores : 18
 siblings : 36
 physical 0: cores 0 1 2 3 4 8 9 10 11 16 17 18 19 20 24 25 26 27
 physical 1: cores 0 1 2 3 4 8 9 10 11 16 17 18 19 20 24 25 26 27

From lscpu:
 Architecture: x86_64
 CPU op-mode(s): 32-bit, 64-bit
 Byte Order: Little Endian
 CPU(s): 72
 On-line CPU(s) list: 0-71
 Thread(s) per core: 2
 Core(s) per socket: 18
 Socket(s): 2
 NUMA node(s): 4
 Vendor ID: GenuineIntel
 CPU family: 6
 Model: 85
 Model name: Intel(R) Xeon(R) Gold 6240M CPU @ 2.60GHz
 Stepping: 7
 CPU MHz: 2600.000
 CPU max MHz: 3900.0000
 CPU min MHz: 1000.0000

(Continued on next page)
Cisco Systems
Cisco UCS B200 M5 (Intel Xeon Gold 6240M, 2.60GHz)

CPU2017 License: 9019
Test Sponsor: Cisco Systems
Tested by: Cisco Systems

SPECratenumber_int_base = 227
SPECratenumber_int_peak = Not Run

Test Date: Aug-2019
Hardware Availability: Apr-2019
Software Availability: May-2019

Platform Notes (Continued)

BogoMIPS: 5200.00
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 1024K
L3 cache: 25344K
NUMA node0 CPU(s): 0-2,5,6,9,10,14,15,36-38,41,42,45,46,50,51
NUMA node1 CPU(s): 3,4,7,8,11-13,16,17,39,40,43,44,47-49,52,53
NUMA node2 CPU(s): 18-20,23,24,27,28,32,33,34-35,57,58,61,62,65-67,70,71
NUMA node3 CPU(s): 21,22,25,26,29-31,34,35,55,56,59,59,60,63,64,68,69
Flags: fpu vme de pse tsc msr pae mce cmov pat pse36 c compiler_safe ds acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 sse3


 \approx 35\% \cdot \left(V_{out,setpoint} + \frac{V_{AC,max(pk)} + V_{margin,FET}}{N}\right)$,

$$V_{r(diode),max} \approx 135\% \cdot \left(V_{out,setpoint} + \frac{V_{AC,max(pk)} + V_{margin,FET}}{N}\right) = 135\% \cdot \left(54 + \frac{\sqrt{2} \cdot 305 + 90}{3.2}\right)$$

$$V_{r(diode),max} \approx 292.81 \, V$$

$$I_{sec(pk),max} \approx I_{pri(pk),max} \cdot \frac{N_p}{N_z} = 2.606 \cdot \frac{32}{10}$$

(12)

$$I_{sec(pk),max} \approx 8.34 \, A$$

Based on the above, a secondary main output diode with repetitive reverse voltage rating $V_{RRM} = 300 \, V$ is selected. To minimize its switching and conduction losses, the selected diode also has the properties of hyper-fast recovery speed and low forward voltage drop at $I_{sec(pk),max}$.

Additionally, a RC secondary snubber network, e.g., 10 Ω resistor in series with 150 pF capacitor, is deployed across the secondary main output diode, to suppress the diode reverse voltage spike and the EMI.
5 CS resistor and GD pin-related design

Figure 5 shows the connections of the current sense (CS) resistor $R_{CS}$, gate resistor $R_G$ and gate source resistor $R_{GS}$.

![Figure 5 GD pin, CS pin, R_{CS}, R_G and R_{GS} connections](image)

Based on the CS pin voltage across $R_{CS}$, the MOSFET current can be measured.

The recommended minimum CS resistor value $R_{CS,\text{min}}$ is defined and calculated as:

$$R_{CS,\text{min}} = \frac{0.45}{I_{pri(pk),\text{max}}} = \frac{0.45}{2.606} = 0.173 \Omega$$  \hspace{1cm} (13)

The recommended maximum CS resistor value $R_{CS,\text{max}}$ is defined and calculated as:

$$R_{CS,\text{max}} = \frac{0.54}{I_{pri(pk),\text{max}}} = \frac{0.54}{2.606} = 0.207 \Omega$$  \hspace{1cm} (14)

Based on the calculation results above, CS resistor $R_{CS} = 0.2 \Omega$ is selected in this design example.

$R_G$ is to damp the gate-rise oscillation, and $R_{GS}$ is to ensure the MOSFET gate has relatively low impedance to prevent it from being switched on undesirably. $R_G = 10 \Omega$ and $R_{GS} = 20 \text{k}\Omega$ are selected in this design example.

The gate-drive peak voltage $V_{GD,pk}$ is typically 12 V with sufficient $V_{CC}$ voltage supply. To achieve a good balance of switching loss and EMI, the gate voltage rising slope can be controlled by configuring the gate driver peak source current parameter $I_{GD,pk}$ (configurable range: 30 mA to 118 mA). This saves two components (see $D_{\text{fastoff}}$, $R_{\text{slowon}}$ in Figure 6), which are conventionally added for the same purpose.

![Figure 6 Gate-drive voltage rising slope control with $I_{GD,pk}$ parameterization for component saving](image)

With the high-speed switching characteristics of CoolMOS™ P7 MOSFET, it is recommended to configure the $I_{GD,pk}$ parameter in the range of 30 mA to 49 mA.

As a result, $I_{GD,pk} = 30 \text{ mA}$ is selected in this design example.
6 Input voltage parameters for operation, start-up and protection

The lowest operational input voltage parameter $V_{in,low}$ and the highest operational input voltage parameter $V_{in,high}$ can be defined and calculated as:

$$V_{in,low} = a \cdot V_{AC,\text{min}}$$

$$V_{in,high} = b \cdot V_{AC,\text{max}}$$

Where $a$ is recommended to be between 0.9 and 0.95, and $b$ is recommended to be between 1.05 and 1.10.

Taking $a = 0.91$ and $b = 1.07$,

$$V_{in,low} = 82 \, V_{\text{rms}}$$

$$V_{in,high} = 326 \, V_{\text{rms}}$$

$EN_{OVP,\text{In}}$ parameter refers to the enable switch for maximum input voltage start-up check and input OVP, based on $V_{\text{in,start,max}}$ and $V_{\text{inOV}}$ levels, respectively. $EN_{OVP,\text{In}} = \text{Enabled}$ is selected in this design example.

$EN_{UVP,\text{In}}$ parameter refers to the enable switch for minimum input voltage start-up check and input UVP, based on $V_{\text{in,start,min}}$ and $V_{\text{inUV}}$ levels, respectively. $EN_{UVP,\text{In}} = \text{Enabled}$ is selected in this design example.

$V_{\text{in,start,max}}$ parameter refers to the maximum input voltage level setting for start-up, which is recommended to be configured as $V_{in,high}$. Hence, $V_{\text{in,start,max}} = 326 \, V_{\text{rms}}$ is selected in this design example. $V_{\text{inOV}}$ parameter refers to the input OVP level setting, which is recommended to be:

$$V_{\text{inOV}} \geq V_{\text{in,start,max}} \cdot 107\% = 349 \, V_{\text{rms}}$$

(17)

$V_{\text{in,start,min}}$ parameter refers to the minimum input voltage level setting for start-up, which is recommended to be configured as $V_{in,low}$. Hence, $V_{\text{in,start,min}} = 82 \, V_{\text{rms}}$ is selected in this design example. $V_{\text{inUV}}$ parameter refers to the input UV (brown-out) protection level setting, which is recommended as:

$$V_{\text{inUV}} \leq V_{\text{in,start,min}} \cdot 93\% = 76 \, V_{\text{rms}}$$

(18)

Based on the above, $V_{\text{inOV}} = 350 \, V_{\text{rms}}$ and $V_{\text{inUV}} = 70 \, V_{\text{rms}}$ are selected in this design example.

The input voltage protections (based on $V_{\text{inOV}}$ and $V_{\text{inUV}}$) in ABM can be optionally enabled with $EN_{\text{VIN,ABM}}$ parameter. If $EN_{\text{VIN,ABM}}$ is enabled, the enable switches for $V_{\text{inOV}}$ and $V_{\text{inUV}}$ protections in ABM are respectively based on $EN_{OVP,\text{In}}$ and $EN_{UVP,\text{In}}$. In this design example, $EN_{\text{VIN,ABM}} = \text{Enabled}$ is selected. The input OVP blanking period number parameter $t_{\text{inOV,blank}} = 1$ is recommended and selected in this design example.
# HV pin-related design

As shown in Figure 8, HV series resistor \( R_{HV} \) is connected from the HV pin to the cathodes of HV diode \( D_{HV1} \) and \( D_{HV2} \), while bridge rectifier AC input should be applied across the \( D_{HV1} \) anode and \( D_{HV2} \) anode.

A high voltage capacitor \( C_{HV} \) should also be connected between the HV pin and ground, to filter the switching noise for a robust HV pin line synchronization. In addition, \( C_{HV} \) also improves the input voltage surge and ESD capability of the HV pin.

The repetitive reverse voltage rating \( V_{RRM} = 1000 \text{ V} \) for \( D_{HV1} \) and \( D_{HV2} \) is recommended and selected in this design example, to ensure good reliability of the diodes against input voltage surge.

![Figure 8](image)

**


, CA 94022 (415) 948-6533.
- SOUTHERN CALIFORNIA, ARIZONA: Crown Electronics, 1146 Collins Street, No. Hollywood, CA 91601 (213) 877-3550

INFORMATION RETRIEVAL NUMBER 3

Electronic Design 24, November 22, 1975
NEWS
23 News Scope
29 Washington Report
50 Instrument '75—a special issue featuring current trends in instrumentation. Topics covered include: microprocessors in instruments; computer and calculator-based instrumentation; the latest in LSI testers; what's new in function generators; instruments in the nonelectronics industry and new multifunction instruments. In addition, there are engineering management interviews with Bill Terry and Jack Lieberman of Hewlett-Packard and Henk Bodt of Philips Test & Measurement.

TECHNOLOGY
37 MICROPROCESSOR DESIGN
112 Phase-meter specs can fool you, unless you consider the input signal before buying. First, know your application, then see how the meter responds.
120 To test hybrid PC boards, with mixed analog and digital circuits, requires a versatile test system. The practical choice narrows down to four types.
128 Test semiconductors automatically with a computer. With a precision interface, you can accurately force voltage or current and measure response.
134 Avoid I^2D0 measurements and you will lighten your test load. But if you must measure this vague transistor parameter, here's how to do it faster.
138 Take oddball pulses in stride. A new method, the pulse-width synthesizer, lets you accurately measure the widths of unpredictably shaped pulses.
146 Ideas for Design:
FET analog-switch circuit provides 63-dB on-off ratio. Capacitor drops voltage with little heat for low-cost, low-voltage power supply. Crystal control of a one-shot ensures accurate pulse-width output.

PRODUCTS
162 Modules & Subassemblies: Deglitching modules attenuate spikes on current-output d/a's by over 70 dB.
171 Data Processing: Full APL computer delivers mainframe power in mini size.
174 Data Processing: OEM mini line offers core or MOS memory.
186 Power Sources: Modular sources carry high-MTBF label.
178 Discrete Semiconductors
190 Components
196 Packaging & Materials

DEPARTMENTS
109 Editorial: The politicians
7 Across the Desk
209 Evaluation Samples
210 New Literature
214 Bulletin Board
214 Vendors Report
220 Advertisers' Index
222 Product Index
224 Information Retrieval Card
You can go into production of higher density memory systems confidently now that Intel's new 2104 16-pin, 4096-bit dynamic RAM is in stock at Intel distributors, and readily available in OEM quantities.

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Intel's 16-pin RAM assures you fast, reliable parts as well as delivery in volume. The Intel 2104 is based on the proven single-transistor cell design of the Intel 2107B, the highest performance 22-pin 4K MOS RAM. Like the 2107B, the 2104 chip is much smaller than other 4K RAM chips produced today.

The fastest available 16-pin 4K RAMs are also in the 2104 series. Our 2104-2 guarantees an access time of only 250 nanoseconds and a cycle time of 375 nanoseconds over the full 0 to 70°C operating temperature range.

To keep system costs low, the 2104 operates on standard -5, +5 and +12V power supplies, and TTL I/O levels. All inputs including clock

INTEL'S STANDARD 4K RAM FAMILY
Max. Access Time (ns), 0-70°C
Min. Cycle Time (ns), 0-70°C

Part Number
Pins
Read or write

D2104-2
16
250

D2104-4
16
300

D2104
16
350

2107B
22
200

2107B-2
22
220

2107B-4
22
270

2107B-6
22
350

inputs are fully TTL compatible.

Overall system advantages of the 2104 are detailed in a new application brief, "Which Way for 4K... 16, 18, or 22 Pin?" It explains why the 16-pin 2104 is best for very compact systems such as minicomputers, microcomputers, terminals, business equipment, scientific calculators and anywhere high density is needed.

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For your copy of "Which Way for 4K..." or data sheets on any of our 4K RAMs write: Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051.

intel delivers.
Try this with a CRT or a digital display

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5, where causing the silent mode to be overridden comprises:
changing a setting of the user device based on receiving the first message including the first prompt,
the setting relating to the silent mode; and
where providing the first alert and the second alert comprises:
providing the first alert and the second alert based on changing the setting of the user device.

18. The method of claim 15, where providing the first alert and the second alert comprises:
providing an audible alert by playing an audio file; and
providing a visual alert by running an application,
the application activating a light emitting diode associated with the user device.
19. The method of claim 15, where the first message includes the text of the first prompt and additional text.
20. (canceled)
21. The user device of claim 1, where the first alert is audible and the second alert is visual.
22. The user device of claim 1, where the one or more processors are further to:
   determine that a peripheral device is connected to the user device; and
   where the one or more processors, when providing the first alert and the second alert, are to:
   provide the first alert and the second alert based on determining that the peripheral device is connected
   to the user device.
23. The non-transitory computer-readable medium of claim 8, where the first alert is audible and the second alert
is visual.
24. The method of claim 15, where the first alert is audible and the second alert is visual.
25. The method of claim 15, further comprising:
   determining that a peripheral device is connected to the user device; and
   where providing the first alert and the second alert comprises:
   providing the first alert and the second alert based on determining that the peripheral device is connected
   to the user device.

* * * * *<|endoftext|>Cisco Catalyst 3850 Series and Cisco Catalyst 3650 Series Switches Best Practices Guide

First Published: November 30, 2015
Last Updated: December 14, 2015

Cisco Systems, Inc.
www.cisco.com

Cisco has more than 200 offices worldwide. Addresses, phone numbers, and fax numbers are listed on the Cisco website at www.cisco.com/go/offices.
Preface vii

Audience iii-vii

Conventions vii

Obtaining Documentation and Submitting a Service Request viii

Ease of Deployment 1-1

Purpose 1-1

Configuration Tool 1-2

Catalyst Switch Configuration Best Practices 1-2

LAN Access Switch Topology 1-4

Switch Address Plan 1-5

Initial Switch Configuration 2-7

Purpose 2-7

Prerequisites 2-7

Identify Configuration Values 2-8

Assign Initial Management Information 2-8

Configure the Hostname for Switch Identification 2-9

Configure Secure HTTPS and Secure Shell for Secure LAN Management 2-9

Configure SNMP for Remote Management 2-10

Configure Local Login and Password for Switch Access 2-10

Configure Centralized User Authentication Through TACACS+ 2-10

Assign an IP Address to the Switch 2-11

Configure the Management IP Address on an Out-of-Band Interface 2-12

Configure the Management IP Address on an In-Band Interface 2-14

Create a Management VLAN in Hardware 2-15

Verify Basic Switch Configuration 2-17

Show Running Configuration for Initial Management Information 2-17

Switch Stack Update 3-21

Purpose 3-21

Prerequisites 3-21

Identify Configuration Values 3-22
LAN Access Switch Topology with Configured FTP Server  3-22
Performing the Stack Update  3-23
   Obtain the Switch Software Image  3-23
   Check the Software Version on the Stack Members  3-23
   Configure the Switch to Run in Install Mode  3-24
   Download the Switch Image from Cisco.com to a FTP Server  3-25
   Update the Switch Stack Image  3-27
   Enable Switch Image Auto-Upgrade  3-27
   Verify that Stack Members Are Running the Same Software Image  3-28

Global System Configuration  4-29
Purpose  4-29
Prerequisites  4-29
Identify Configuration Values  4-29
Assign Global Configuration Information  4-30
   Configure High Availability on the Switch Stack  4-31
   Configure VTP Transparent Mode  4-31
   Enable Rapid Per-VLAN Spanning Tree  4-32
   Configure BPDU Guard for Spanning-Tree PortFast Interfaces  4-32
   Configure ULDL to Detect Link Failure  4-33
   Configure an Access List to Limit Switch Access  4-33
   Configure System Clock and Console Timestamps  4-34
   Configure DHCP Snooping Security Features  4-34
   Configure ARP Inspection  4-34
   Configure EtherChannel Load Balancing  4-35
   Create Access Layer VLANs  4-35
   Create IPv6 First Hop Security Policies  4-35
   Increase the TFTP Block Size  4-36
   Enable New Members to Automatically Update to the Switch Stack Image  4-36
   Verify Global Switch Configuration  4-37
Show Running Configuration For Global Management Information  4-37

Uplink Interface Connectivity  5-41
Purpose  5-41
Prerequisites  5-41
Restrictions  5-41
Identify Configuration Values  5-42
LAN Access Switch Topology with Uplinks to a Distribution Switch or Distribution Router  5-43
Configure Uplink Interface Connectivity  5-44
Preface

Audience

This document is written for managing the Cisco Catalyst 3850 Series Switches and the Cisco 3650 Series switches and switch stacks in their network. A basic understanding of Ethernet networking is expected. Cisco Certified Network Associate level (CCNA) knowledge is helpful, but not required.

Conventions

This document uses the following conventions:

Convention
Indication

italic blue font
Example configuration values that are replaced with reader values.

bold font
Commands and keywords and user-entered CLI appear in bold font.

italic font
Document titles, new or emphasized terms, and arguments for which you supply values are in italic font.

[ ]
• Default responses to system prompts are in square brackets.

• Elements in square brackets are optional.

{x
y

[x
y

string
A nonquoted set of characters. Do not use quotation marks around the string, or the string will include the quotation marks.

courier font
Terminal sessions and information the system displays appear in courier font.

< >
Nonprinting characters such as passwords are in angle brackets.

!, #
An exclamation point (!) or a pound sign (#) at the beginning of a line of code indicates a comment line.

Note

Means reader take note. Notes contain helpful suggestions or references to material that is not covered in the manual.
The tips information might not be troubleshooting or even an action, but could be useful information, similar to a Timesaver.

You can save time by performing the action described in the paragraph.

Obtaining Documentation and Submitting a Service Request

For information on obtaining documentation, using the Cisco Bug Search Tool (BST), submitting a service request, and gathering additional information, see What’s New in Cisco Product Documentation at: http://www.cisco.com/c/en/us/td/docs/general/whatsnew/whatsnew.html.

Subscribe to What’s New in Cisco Product Documentation, which lists all new and revised Cisco technical documentation as an RSS feed and deliver content directly to your desktop using a reader application. The RSS feeds are a free service.
Ease of Deployment

This document describes best practices for deploying your Cisco Catalyst 3850 Series and Cisco Catalyst 3650 Series switches.

Note

Unless otherwise noted, the term switch refers to a standalone Catalyst 3850 switch, a Catalyst 3650 switch, or a switch stack.

A Cisco switch deployment best practice is a preferred configuration method to employ on your Catalyst switches. It is a proven and tested way to improve network security, performance, and availability.

A best practice configuration includes an explanation of why you should perform a given task and a sample snapshot of a full running configuration that you can extrapolate for your specific scenario.

Tip

Use the configuration recommendations in this document as a template for your switch deployments.

Note

Many


, blue
   gray scale data to the plurality of data lines;
   a direct current to direct current (DC-DC) converter for
   outputting a DC voltage for carrying out a bend transition
   on the OCB liquid crystal;
   a switch for selecting the output voltage of the DC-DC
   converter and a common voltage and transferring the
   voltages to the common electrode;
   a light source controller for controlling red, green, and
   blue light emitting diodes to sequentially emit light to
   the liquid crystal display panel; and
   a timing controller for controlling operations of the scan
   driver, the source driver, the switch, and the light
   source controller,
wherein one frame is divided into red, green, and blue
fields and the switch applies the output voltage of the
DC-DC converter to the common electrode before a
start of each field to reset the OCB liquid crystal.
10. The LCD of claim 9, wherein the output voltage of the
    DC-DC converter is 15V to 30V.
11. The LCD of claim 9, wherein the source driver does
    not apply the red, green, and blue gray scale data when the
    switch selects the output voltage of the DC-DC converter.
12. The LCD of claim 9, wherein the OCB liquid crystal
    has an optical transmittance of zero when the OCB liquid
    crystal is reset.
13. The LCD of claim 9, wherein each pixel comprises:
    a switching transistor for transferring the red, green, and
    blue gray scale data transferred via the data lines to the
    pixel electrode in response to the scan signal of the scan
    lines; and
    a storage capacitor for storing the gray scale data.
14. A liquid crystal display device (LCD), comprising:
    a liquid crystal display panel having a plurality of pixels,
    each pixel being positioned at each intersection
    between a plurality of scan lines and a plurality of data
    lines and including a liquid crystal capacitor composed
    of a common electrode, a pixel electrode, and an
    optically compensated birefringence (OCB) liquid
    crystal;
    a scan driver for applying a scan signal to the plurality of
    scan lines;
    a source driver for applying gray scale data to the plurality
    of data lines;
    a direct current to direct current (DC-DC) converter for
    outputting a DC voltage for carrying out a bend transition
    on the OCB liquid crystal;
    a switch for selecting the output voltage of the DC-DC
    converter and a common voltage and transferring the
    voltages to the common electrode;
    a light source controller for controlling a backlight for
    emitting light to the liquid crystal display panel; and
    a timing controller for controlling operations of the scan
    driver, the source driver, the switch, and the light
    source controller,
wherein the switch applies the output voltage of the
DC-DC converter to the common electrode to reset the
OCB liquid crystal before the gray scale data are
applied to the plurality of pixels.
15. The LCD of claim 14, wherein the output voltage of the
    DC-DC converter is 15V to 30V.
16. The LCD of claim 14, wherein the source driver does not
    apply the gray scale data when the switch selects the
    output voltage of the DC-DC converter.
17. The LCD of claim 14, wherein the OCB liquid crystal
    has an optical transmittance of zero when the OCB liquid
    crystal is reset.
18. The LCD of claim 14, wherein the backlight comprises
    one of a white light emitting diode (LED) and a cold
    cathode fluorescence lamp (CCFL) which emits white light.
19. The LCD of claim 18, further comprising red, green, and
    blue color filters positioned on the common electrode of
    the plurality of pixels for filtering light emitted from the
    backlight.
20. The LCD of claim 14, wherein each pixel includes:
    a switching transistor for transferring the gray scale data
    transferred via the data lines to the pixel electrode in
    response to the scan signal of the scan lines; and
    a storage capacitor for storing the gray scale data.
21. A method of driving a liquid crystal display device
    (LCD) including a plurality of pixels having an optically
    compensated birefringence (OCB) liquid crystal positioned
    between a common electrode to which a common voltage is
    applied and a pixel electrode to which gray scale data are
    applied, a direct current to direct current (DC-DC) converter
    outputting a voltage for carrying out a bend transition on
    the OCB liquid crystal at a fast speed, and a backlight outputting
    light to the plurality of pixels, the method comprising:
   (a) applying a voltage to the OCB liquid crystal from the
       DC-DC converter to carry out the bend transition on the
       OCB liquid crystal at an initial start of the LCD;
   (b) applying the gray scale data of a frame to the pixel
       electrode in the frame;
   (c) applying a voltage to the common electrode from the
       DC-DC converter to reset the OCB liquid crystal after
       the step (b);
   (d) applying the gray scale data of a second frame to the
       pixel electrode in the second frame; and
   (e) repeating the steps (b) to (d).
22. The method of claim 21, wherein the output voltage of the DC-DC converter is 15V to 30V.

23. The method of claim 21, wherein the gray scale data are not applied in the step (c).

24. The method of claim 21, wherein the OCB liquid crystal has an optical transmittance of zero when the OCB liquid crystal is reset.

25. The method of claim 21, wherein the backlight emits light during the steps (b) to (d).

26. The method of claim 21, wherein the backlight comprises a red light emitting diode (LED), a green LED, and a blue LED which sequentially emit red, green, and blue light.

27. The method of claim 21, wherein the backlight comprises one of a white light emitting diode (LED) and a cold cathode fluorescence lamp (CCFL) which emits white light.

28. The method of claim 27, further comprising red, green, and blue color filters positioned on the common electrode of the plurality of pixels and filtering light emitted from the backlight.

29. A method of driving a liquid crystal display device (LCD) including a plurality of pixels having an optically compensated birefringence (OCB) liquid crystal positioned between a common electrode to which a common voltage is applied and a pixel electrode to which red, green, and blue gray scale data are sequentially applied, a direct current to direct current (DC-DC) converter outputting a voltage for carrying out a bend transition on the OCB liquid crystal at a fast speed, and a backlight having red, green, and blue light sequentially transmitted to each of the pixels, the method comprising:

   (a) applying a voltage to the OCB liquid crystal from the DC-DC converter to carry out a bend transition on the OCB liquid crystal at an initial start of the LCD;

   (b) dividing one frame into red, green, and blue fields, and applying the red gray scale data to the pixel electrode in the red field;

   (c) applying a voltage to the common electrode from the DC-DC converter to reset the OCB liquid crystal after the step (b);

   (d) applying the green gray scale data to the pixel electrode in the green field;

   (e) applying a voltage to the common electrode from the DC-DC converter to reset the OCB liquid crystal after the step (d);

   (f) applying the blue gray scale data to the pixel electrode in the blue field;

   (g) applying a voltage to the common electrode from the DC-DC converter to reset the OCB liquid crystal after the step (f); and

   (h) repeating the steps (b) to (g).

30. The method of claim 29, wherein the output voltage of the DC-DC converter is 15V to 30V.

31. The method of claim 29, wherein the red, green, and blue gray scale data are not applied in the steps (c), (e), and (f).

32. The method of claim 29, wherein the OCB liquid crystal has an optical transmittance of zero when the OCB liquid crystal is reset.

33. The method of claim 29, wherein the backlight emits light during the steps (b) to (h).

34. The method of claim 29, wherein the backlight comprises a red light emitting diode (LED), a green LED, and a blue LED which sequentially emit red, green, and blue light.

35. A method of driving a liquid crystal display device (LCD) including a plurality of pixels having an optically compensated birefringence (OCB) liquid crystal positioned between a common electrode to which a common voltage is applied and a pixel electrode to which gray scale data are applied, a direct current to direct current (DC-DC) converter outputting a voltage for carrying out a bend transition on the OCB liquid crystal at a fast speed, and a backlight outputting light to the plurality